-- -- Shift Register -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shreg is port ( d, clk, reset : in std_logic; q : out std_logic); end shreg; architecture behav of shreg is signal t : std_logic_vector(3 downto 0); begin process (clk, d) begin if reset='1' then t <= "0000"; end if; if (clk'event and clk = '1') then -- rising clock edge t <= t(2 downto 0) & d; q <= t(3); end if; end process; end behav;