LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY cont8_tb IS END cont8_tb; ARCHITECTURE testbench OF cont8_tb IS COMPONENT cont8 PORT(clock, reset, set: IN STD_LOGIC; outa: OUT STD_LOGIC_VECTOR(0 to 7)); END COMPONENT; signal clk,rst,set: std_logic; signal oa: std_logic_vector(0 to 7); BEGIN uut: cont8 PORT MAP (clk,rst,set,oa); clock_p: PROCESS BEGIN clk <= '0'; WAIT FOR 50 ns; clk <= '1'; WAIT FOR 50 ns; END PROCESS; reset_p: PROCESS BEGIN rst <= '1'; wait for 10 ns; rst <= '0'; WAIT FOR 220 ns; rst <= '1'; WAIT FOR 10 ns; END PROCESS; set_p: PROCESS BEGIN set <= '0'; WAIT FOR 320 ns; set <= '1'; WAIT FOR 50 ns; END PROCESS; END testbench;