entity DEC_BCD_7_TB is end DEC_BCD_7_TB; architecture test of DEC_BCD_7_tb is component DEC_BCD_7 is port (X: in bit_vector(0 to 3); Z: out bit_vector (0 to 6)); end component; signal X_s : bit_vector(0 to 3); signal Z_s : bit_vector(0 to 6); begin uut : DEC_BCD_7 port map (X_s, Z_s); X_p: process begin X_s <= "0000"; wait for 10 ns; X_s <= "0001"; wait for 10 ns; X_s <= "0010"; wait for 10 ns; X_s <= "0011"; wait for 10 ns; X_s <= "0100"; wait for 10 ns; X_s <= "0101"; wait for 10 ns; X_s <= "0110"; wait for 10 ns; X_s <= "0111"; wait for 10 ns; X_s <= "1000"; wait for 10 ns; X_s <= "1001"; wait for 10 ns; X_s <= "1010"; wait for 10 ns; X_s <= "1011"; wait for 10 ns; X_s <= "1100"; wait for 10 ns; X_s <= "1101"; wait for 10 ns; X_s <= "1110"; wait for 10 ns; X_s <= "1111"; wait for 10 ns; end process; end test;