entity DEC24_TB is end DEC24_TB; architecture BEHAV of DEC24_TB is component DEC24 port ( A, B: in bit; Z: out bit_vector (0 to 3)); end component; signal A_S, B_S: bit; signal Z_S: bit_vector (0 to 3); begin uut: DEC24 port map (A_S, B_S, Z_S); A_p: process -- andamento del segnale A_S begin A_S <= '0'; wait for 10 ns; A_S <= '1'; wait for 10 ns; end process; B_p: process -- andamento del segnale B_S begin B_S <= '0'; wait for 20 ns; B_S <= '1'; wait for 20 ns; end process; end BEHAV;