-- -- Shift Register Testbench -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shreg_tb is end shreg_tb; architecture test of shreg_tb is component shreg is port ( d, clk : in std_logic; q : out std_logic); end component; signal d_s, clk_s, q_s : std_logic; begin uut: shreg port map (d_s, clk_s, q_s); d_p: process begin d_s <= '0'; wait for 15 ns; d_s <= '1'; wait for 20 ns; d_s <= '0'; wait for 25 ns; d_s <= '1'; wait for 10 ns; end process; clk_p: process begin clk_s <= '0'; wait for 10 ns; clk_s <= '1'; wait for 10 ns; end process; end test;