library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY cont8 IS PORT(clock, reset: IN STD_LOGIC; outa: OUT STD_LOGIC_VECTOR(0 to 7)); END cont8; ARCHITECTURE rtl OF cont8 IS signal t: std_logic_vector(0 to 7); BEGIN PROCESS(clock, reset) BEGIN IF (reset = '1' ) THEN t(0 to 7) <= "00000000"; ELSE IF(clock'event and clock = '1' ) THEN t <= t + "00000001"; END IF; end if; END PROCESS; outa <= t; END rtl;