entity latch_tb is end latch_tb; architecture test of latch_tb is component latch is port (d, enable: in bit; q: out bit); end component; signal d_s,e_s,q_s : bit; begin uut: latch port map (d_s, e_s, q_s); d_p: process begin d_s <= '1'; wait for 10 ns; d_s <= '0'; wait for 20 ns; d_s <= '1'; wait for 20 ns; d_s <= '0'; wait for 10 ns; end process; e_p: process begin e_s <= '1'; wait for 20 ns; e_s <= '0'; wait for 10 ns; e_s <= '1'; wait for 10 ns; e_s <= '0'; wait for 20 ns; end process; end test;