entity REG4_TB is end REG4_TB; architecture TEST of REG4_TB is component REG4 is port ( d: in bit_vector (0 to 3); clk: in bit; q: out bit_vector (0 to 3)); end component; signal d_s, q_s: bit_vector (0 to 3); signal clk_s: bit; begin u1: REG4 port map (d_s,clk_s,q_s); clk_p: process -- segnale di clock begin clk_s <= '0'; wait for 10 ns; clk_s <= '1'; wait for 10 ns; end process; d_p: process -- segnale d (ingresso) begin d_s <= "0000"; wait for 15 ns; d_s <= "0001"; wait for 27 ns; d_s <= "0011"; wait for 21 ns; d_s <= "0111"; wait for 12 ns; d_s <= "1111"; wait; end process; end TEST;