-- -- Full adder -- entity fulladd is port (i0, i1 : in bit; -- input ci : in bit; -- riporto in input s : out bit; -- somma (output) co : out bit); -- riporto in output end fulladd; architecture rtl of fulladd is begin -- calcolo della somma s <= i0 xor i1 xor ci; -- calcolo del riporto co <= (i0 and i1) or (i0 and ci) or (i1 and ci); end rtl;