entity REG4 is port ( d: in bit_vector (0 to 3); clk: in bit; q: out bit_vector (0 to 3)); end REG4; architecture STRUCT of REG4 is component FF_D port (d, clk: in bit; q: out bit); end component; begin u1: FF_D port map (d(0),clk,q(0)); u2: FF_D port map (d(1),clk,q(1)); u3: FF_D port map (d(2),clk,q(2)); u4: FF_D port map (d(3),clk,q(3)); end STRUCT;