library ieee; USE ieee.std_logic_1164.all; entity FF_set_reset is port ( Reset, Set, Clk, D : in std_logic; Q : out std_logic); end FF_set_reset; architecture behaviour of FF_set_reset is -- set sincrono -- reset asincrono begin process (Reset,Clk) begin if (Reset='1') then Q <= '0'; else if (clk'event and clk='1') then if (Set='1') then Q <= '1'; else Q <= D; end if; end if; end if; end process; end behaviour;