-- -- Full adder a 8 bit -- entity fulladd8 is port (i0, i1 : in bit_vector(7 downto 0); -- input ci : in bit; -- riporto in input s : out bit_vector(7 downto 0); -- somma (output) co : out bit); -- riporto in output end fulladd8; architecture struct of fulladd8 is component fulladd port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); end component; signal t : bit_vector(0 to 8); begin t(0) <= ci; fa0: fulladd port map (i0(0), i1(0), t(0), s(0), t(1)); fa1: fulladd port map (i0(1), i1(1), t(1), s(1), t(2)); fa2: fulladd port map (i0(2), i1(2), t(2), s(2), t(3)); fa3: fulladd port map (i0(3), i1(3), t(3), s(3), t(4)); fa4: fulladd port map (i0(4), i1(4), t(4), s(4), t(5)); fa5: fulladd port map (i0(5), i1(5), t(5), s(5), t(6)); fa6: fulladd port map (i0(6), i1(6), t(6), s(6), t(7)); fa7: fulladd port map (i0(7), i1(7), t(7), s(7), t(8)); co <= t(8); end struct;