entity dec_7_esa_tb is
end dec_7_esa_tb;
architecture testbench of dec_7_esa_tb is
component dec_7_esa is
port ( X: in bit_vector (3 downto 0);
a, b, c, d, e, f, g: out bit);
end component;
signal X: bit_vector (3 downto 0);
signal Z: bit_vector (1 to 7);
signal ris : bit := '0';
begin
uut : dec_7_esa port map (X, Z(1), Z(2), Z(3), Z(4), Z(5), Z(6), Z(7));
-- ris deve valere 0 finche' il componente si comporta secondo le specifiche
ris <= '0' when ((X ="0000" and Z="1110111") or
(X ="0001" and Z="0010010") or
(X ="0010" and Z="1011101") or
(X ="0011" and Z="1011011") or
(X ="0100" and Z="0111010") or
(X ="0101" and Z="1101011") or
(X ="0110" and Z="1101111") or
(X ="0111" and Z="1010010") or
(X ="1000" and Z="1111111") or
(X ="1001" and Z="1111011") or
(X ="1010" and Z="1111110") or
(X ="1011" and Z="0101111") or
(X ="1100" and Z="1100101") or
(X ="1101" and Z="0011111") or
(X ="1110" and Z="1101101") or
(X ="1111" and Z="1101100")
)
else '1';
X_p: process
begin
X <= "0000";
wait for 10 ns;
X <= "0001";
wait for 10 ns;
X <= "0010";
wait for 10 ns;
X <= "0011";
wait for 10 ns;
X <= "0100";
wait for 10 ns;
X <= "0101";
wait for 10 ns;
X <= "0110";
wait for 10 ns;
X <= "0111";
wait for 10 ns;
X <= "1000";
wait for 10 ns;
X <= "1001";
wait for 10 ns;
X <= "1010";
wait for 10 ns;
X <= "1011";
wait for 10 ns;
X <= "1100";
wait for 10 ns;
X <= "1101";
wait for 10 ns;
X <= "1110";
wait for 10 ns;
X <= "1111";
wait for 10 ns;
end process;
end testbench;