LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity cont8_sin_load_tb is end cont8_sin_load_tb; architecture testbench of cont8_sin_load_tb is component cont8_sin_load is port (clock : in std_logic; load : in std_logic; X : in std_logic_vector(7 downto 0); Z : out std_logic_vector(7 downto 0) ); end component; signal Z : std_logic_vector (7 downto 0); signal X : std_logic_vector (7 downto 0); signal clock : std_logic; signal load : std_logic; signal ris : std_logic := '0'; signal t : std_logic_vector(7 downto 0); -- valore di comparazione con l'uscita begin uut : cont8_sin_load port map (clock, load, X, Z); -- finche' ris vale 0 tutto dovrebbe andare bene. ris_p : process (clock, load, X, Z) begin if clock'event and clock = '1' then if load = '1' then t <= X - '1'; else t <= Z; end if; end if; if Z = t + '1' then ris <= '0'; else ris <= '1'; end if; end process; load_p : process begin load <= '1'; wait for 8 ns; load <= '0'; wait for 23 ns; load <= '1'; wait for 1 ns; load <= '0'; wait for 10 ns; load <= '1'; wait for 14 ns; load <= '0'; wait for 100 ns; load <= '1'; wait for 24 ns; load <= '0'; wait for 55 ns; load <= '1'; wait for 1 ns; load <= '0'; wait for 12 ns; end process; X_p : process -- un po' di valori a caso begin X <= "00000000"; wait for 3 ns; X <= "01000001"; wait for 5 ns; X <= "00000000"; wait for 11 ns; X <= "01000001"; wait for 9 ns; X <= "00100010"; wait for 9 ns; X <= "10000011"; wait for 2 ns; X <= "01000100"; wait for 9 ns; X <= "00100101"; wait for 7 ns; X <= "00010110"; wait for 9 ns; X <= "10010111"; wait for 9 ns; X <= "01001000"; wait for 9 ns; X <= "10001001"; wait for 9 ns; X <= "00001010"; wait for 9 ns; X <= "01001011"; wait for 9 ns; X <= "00101100"; wait for 9 ns; X <= "11001101"; wait for 9 ns; X <= "01011110"; wait for 9 ns; X <= "11111111"; wait for 9 ns; end process; clock_p : process begin clock <= '1'; wait for 5 ns; clock <= '0'; wait for 5 ns; end process; end testbench;