library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity cont5_as_load is port (clock : in std_logic; load : in std_logic; X : in std_logic_vector(4 downto 0); Z : out std_logic_vector(4 downto 0) ); end cont5_as_load; architecture myarch of cont5_as_load is signal t : std_logic_vector(0 to 4); begin process (clock, load, X) begin if load = '1' then t <= X; elsif (clock'event and clock = '1') then t <= t + "00001"; end if; end process; Z <= t; end myarch;